The number of used gates and lines of RTL code explodes as IC designs are implemented in 65 nm and smaller. IC designers now struggle to manually create the entire design and still meet their aggressive project schedules. CellMath IP is a catalog of silicon-proven, specialized datapath IP that allows your IC designers to implement major blocks of datapath functionality in a fraction of the time that would be required to develop it internally.
Many vendors offer libraries of off-the-shelf IP that are excellent solutions for accelerating the design time of low-value functions. Arithmatica’s focus is just the opposite because our customers are engineering today’s most advanced products that require exemplary datapath designs. CellMath IP provides differentiated datapath IP of high-value functions that will truly make your product stand out. By utilizing our extensive library of proprietary datapath building blocks and silicon architectures, Arithmatica delivers differentiated datapath IP that exactly meets your design requirements but won’t break your budget or delay your project. Customized functionality, fast and affordable.
Arithmatica's datapath IP models and floating point libraries incorporate a variety of proprietary silicon math improvements innovated by our world-class team of mathematicians and IC design engineers. These improvements can be distinguished as:
- Algorithmic
- Montgomery multiplication
- Architectural
- Floating point parallelization
- Internal rounding
- SIMD operations
- Optimization of table-based functions
- Pipeline optimization
- High order compressors
- Fundamental
- Adder carry-propagate
- Multiplier parallel counter
CellMath IP is applicable in graphics, embedded processing, communications, cryptography, consumer and high-performance computing applications. A typical customer engagement begins with the development of a statement of work by one of our solution architects from your design specifications. You supply an executable specification (golden RTL model), a target process library and design requirements for power, area and/or timing. Arithmatica will return a formally verified gate-level Verilog netlist with bit-accurate simulation models, along with scripts to facilitate functional verification and final integration and optimization of the datapath module within your IC design.
You won’t find a better solution for accelerating and differentiating your datapath design. Contact Arithmatica today to learn how we can help reduce the design burden of your datapath design team and assist you in creating truly differentiated products.
