Archived News

PRESS CONTACT
Dan Ganousis
+011 (303) 859-3048

ARCHIVED PRESS RELEASES

20/Jul/2006
Arithmatica's CellMath Designer Datapath Synthesis Tool Selected by ATI for Next Generation Graphics Designs

20/Jul/2006
Mediatek Selects CellMath Designer for Next Generation Multimedia Projects

24/May/2006
Arithmatica Announces Floating Point Library Customer in Advanced 3D Graphics Group

05/Apr/2006
Arithmatica Updates CellMath™ Tools for Power Optimization and Tighter Flow Integration for Verilog Users

10/Jan/2006
Arithmatica expands CellMath tools line with CellMath Optimizer for silicon-efficient delivery of datapath-oriented silicon IP

13/Sep/2005
Arithmatica Expands Global Sales Network to Europe to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs

13/Jun/2005
Arithmatica Expands Global Coverage to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs

30/May/2005
Arithmatica Enters EDA Market with Proven Tools that Boost Silicon Efficiency by up to 40 Percent for Datapath-Intensive Applications

15/Mar/2005
Arithmatica IP Selected by Xilinx for Virtex-4 XtremeDSP™ Slice

03/Feb/2005
Arithmatica Develops Integrated Flow with Cadence Encounter RTL Compiler to Accelerate Design and Verification of Math-Critical Chips

17/May/2004
Arithmatica Expands Business to Japan and Korea

26/Apr/2004
Breakthrough IP from Arithmatica Boosts Silicon Performance, Reduces Chip Area without Changing Design Process

NEWS ARTICLES

27/Apr/2006
EE Times updates list of 60 emerging startups

28/Jan/2005
Tackling Heavyweight DSP Design with Application-Level Math Circuits

07/Dec/2004
Arithmatica's Dave Burow - Promoting honesty as a best policy

19/Sep/2004
Customer Success: Xilinx Virtex™

26/Apr/2004
Faster Processing or Less Power

26/Apr/2004
Nvidia, Xilinx use CellMath, Arithmatica goes to 65-nm

01/Apr/2004
Better Design Promised By Better Math

"We welcome Arithmatica as our newest In-Sequence partner. Our collaboration in low power datapath design will help our common customers to differentiate with power-aware designs. Our continuing joint technology in the RTL modeling area will bring improved predictability at the datapath behavioral modeling stage."

Vic Kulkarni
CEO
Sequence Design