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Cynthesizer™ is the proven leader in SystemC high-level
synthesis since 2002, with hundreds of quality ASIC, SoC and FPGA designs in consumer products worldwide.
Now high-level design gets even better with the introduction of Cynthesizer Ultra™. Cynthesizer Ultra
combines the first-rate synthesis, verification and timing closure of Cynthesizer with the superior datapath
optimization of
CellMath Designer™. The world's largest systems and semiconductor companies use Cynthesizer for
production designs every day - and now things are getting even better!
For designers working primarily in an RTL flow, Forte's CellMath Designer can help you optimize results as
well. CellMath Designer provides the industry's only formally verifiable design flow for complex datapath
designs with reduced area, increased performance, and efficient power utilization. Using advanced datapath
synthesis algorithms, mathematical techniques, and our patented CellMath IP, it optimizes your existing Verilog
RTL designs to give you more competitive results. CellMath Designer works with your existing logic synthesis tools
and can be deployed immediately on existing projects.
For more information, please contact us at
sales@ForteDS.com. We look forward to seeing you next year at DAC.
- The Forte Team -
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